As the degree of integration has been increased and the size for individual devices has been decreased more and more, development for the technique of forming shallow junctions has been made. For example, in order to prevent increase in the sheet resistance of a source and drain diffusion layer caused by formation of the shallow junction, a source and drain stacking structure as shown in FIG. 1 in which silicon 101a and 101b are epitaxially grown selectively on source and drain regions 100a and 100b has been under development in MOS (Metal Oxide Semiconductor) transistors. In the source and drain stacked structure, crystal faces with small surface energy (for example, (311) face, (111) face, etc.) appear as facets 102a and 102b in each of silicon films 101a and 10b deposited on the source and drain regions 100a and 100b, respectively, on the sides of insulating films 103a and 103b. Such facets 102a and 102b form spike-like silicide regions extending through the source and drain regions 100a and 100b, for example, when silicide is formed on the silicon films 101a and 101b. When such spike-like silicide regions are present, leak current may possibly be formed between the source and drain regions 100a and 100b and the substrate 100.
In view of the above, to prevent occurrence of the facets in the silicon film on the source and drain regions, it has been studied to grow an amorphous silicon having no atom arrangement inherent to crystals (long range order) on the source and drain regions. As the concerned technique, a manufacturing technique for MOS transistors described in Japanese Patent Laid-Open Hei 9-82957 is known. In the manufacturing technique described in Japanese Patent Laid-Open Hei 9-82957, as shown in FIG. 2, a great amount of fluorine is left on the surface of an insulating film formed on a semiconductor substrate 200 (oxide films for device isolation 205a, 205b, 205c covering a gate electrode 204), thereby depositing amorphous silicon layers 208a and 208b selectively only on the source and drain regions 207a and 207b as shown in FIG. 3. Then, the amorphous silicon films 208a and 208b are subjected to a heat treatment for solid phase growing to form crystalline silicon films with no facets.
In addition to the MOS transistor described above, hetero-epitaxial base transistors and strained silicon channel transistors are known as the device involving the problem of facet generation.
In a hetero-epitaxial base transistor, since facets 302a and 302b appear at the ends of a silicon germanium film 301 epitaxially grown on a region held between insulating films 305a and 305b as shown in FIG. 4, gaps 303a and 303b are formed between the silicon germanium film 301 and the insulating films 305a and 305b. Such gaps 303a and 303b will lower the reliability of the transistor.
Further, in a strained silicon transistor channel transistor, since facets 403a and 403b appear in a silicon multi-layered film 402 epitaxially grown in an active region 401 held between oxide films for device isolation 400a and 400b as shown in FIG. 5, a transistor forming region is narrowed. Accordingly, the degree of integration of transistors is lowered.